1. Field of the Invention
The present disclosure relates generally to circuit board signal/ground plane structures, and more particularly to impedance-tuning of a signal/ground plane structure that includes a surface pad.
2. Description of Related Art
Electronic assemblies commonly employ one or more printed circuit boards in their construction. Such circuit boards provide mounting points for electronic components and/or for sockets that allow other circuit boards, cables, or device packages to connect to the circuit board. The surface layers of the board include through-hole pads, surface mounting pads, and in many cases some conductive traces, known as microstrip when referenced to an underlying ground plane, that route signals between pads. The internal circuit board layers provide conductive traces, and possibly planar conductive regions, patterned on conductive layers sandwiched between insulating dielectric layers. A typical circuit board may contain anywhere from a few conductive layers to upwards of thirty such layers for complex systems. Conductive traces route signals (and possibly power) from one point on the circuit board to another point on the circuit board. Planar conductive regions are employed for power distribution. Planar conductive regions also serve as reference planes, which when coupled through a dielectric layer to one of the conductive traces or a differential pair of such traces, form stripline transmission lines of specific impedance. Plated through-holes (PTHs) in the circuit board can form mounting points for press-fit devices, allow for signal insertion/extraction to the internal board layers, and can also serve as layer-swapping vias that transfer a signal from a trace on one conductive layer to another trace on another conductive layer.
FIG. 1 contains a perspective view of a partial circuit board assembly 100, illustrating a few features helpful to the understanding of the embodiments described herein. Assembly 100 includes a surface conductive signal layer, and alternating conductive ground planes and conductive signal layers G1, S2, G2, S3, G3, S4, and G4, located within the circuit board, each conductive layer separated from its immediate neighbors by dielectric layers (for clarity, in FIG. 1 the internal conductive layers are indicated only by their positions on the facing edges of the cross-section). On the surface signal layer, end sections of a surface microstrip differential trace pair (D1+, D1−), terminate respectively at two surface primary pads (PP+, PP−). Each primary pad is proximate two configuration option pads, XFP+ and SFP+ for PP+, and XFP− and SFP− for PP−, where in this example “SFP” corresponds to a configuration option for “Small Form-Factor Pluggable” optical transceivers and “XFP” corresponds to a configuration option for “10 Gigabit Small Form-Factor Pluggable” optical transceivers. The + and − XFP pads connect respectively to two PTHs, PTH1+ and PTH1−, which couple the pads to other traces on signal layer S4, interior to the circuit board, that route the signals to an intended XFP destination. The + and − SFP pads connect respectively to two PTHs, PTH2+ and PTH2−, which couple the pads to other traces on signal layer S4 that route the signals to an intended SFP destination.
To configure the circuit board for a desired configuration option, two discrete packages, DP1 and DP2, are mounted between the primary pads and either the SFP or the XFP pads. In FIG. 1, DP1 connects PP+ to SFP+ and DP2 connects PP− to SFP−, configuring the circuit board for SFP operation. To configure the circuit board for XFP operation, DP1 and DP2 are rotated 90 degrees to couple to the XFP pads instead. DP1 and DP2 can contain jumpers, fuses, resistors, DC blocking capacitors, or other discrete components.
The size of each surface pad is determined by the size of the discrete package, mounting tolerances, and the necessity for flow solder bonding regions on the pad at each end of the package. Generally, these requirements dictate a pad that is much larger than the microstrip traces that deliver signals to or from the pad.
The single-ended characteristic impedance of a microstrip trace, for instance D1+, is determined by the coupling of the trace to ground plane G1. A significant factor in this characteristic impedance is the width of the conductor. As the width of each pad is significantly greater than the width of the conductor, a pad's capacitive coupling and characteristic impedance can depart considerably from the characteristic impedance of the trace connected to the pad, causing reflections and signal loss at high frequencies.
FIG. 2 depicts a plan view of a section 200 of circuit board 100, showing only the surface features D1+, PP+, XFP+, PTH1+, SFP+, and PTH2+, and the underlying features on ground plane G1 (shown in hidden lines). On ground plane G1, a through-hole clearance THC1+ allows PTH1+ to pass through the ground plane without shorting. A similar through-hole clearance THC2+ allows PTH2+ to pass through the ground plane without shorting. Three pad clearances, PC1, PC2, and PC3, adjust the impedance of the surface pads PP+, XFP+, and SFP+, respectively, by creating a large central opening in ground plane G1 where it underlies the surface pad.